The present invention relates to improving the performance of logic gates in an integrated circuit, and more particularly, to a combined dynamic logic gate and level shifting circuit.
Semiconductor manufacturers are under increasing pressure to improve the capacity and performance of semiconductor devices. For example, memory devices having an increasing number of individual memory elements are in demand, as well as devices that function at increased operating speeds.
One consequence of this pressure is that all semiconductor operations are under increased scrutiny to determine where performance improvements may be gained. Among the many semiconductor operations being examined are speed, input loading, and the amount of wasted current.
Digital logic circuits, including complementary metal-oxide-semiconductor (CMOS) circuits, have traditionally suffered from high input loading requirements and current waste. For example, circuits formed with classic logic techniques, such as the NAND gate of FIG. 1 (described in more detail below), are generally simple, but require high input loading and waste current during transitioning between output states. In order to have a high output drive strength, the transistors in a simple classic logic circuit must generally be physically large. Such a configuration requires that the inputs must also be driven by a relatively large device. Also, in classic logic circuits no attempt is made to limit the supply current spikes that flow through the transistors when, during transitions from one output state to another, all transistors are switched simultaneously.
One approach to solving the input loading and current waste problems is to use a dynamic logic gate topology as represented by the AND gate of FIG. 3. In FIG. 3, which is described in more detail below, the arrangement of dynamic logic circuits employs non-overlapping output transitioning and avoids simultaneous switching of all transistors to avoid current waste. Non-overlapping output transitioning is accomplished by configuring the circuit such that one of VDD and ground may be connected to the output, but never both at the same time. Dynamic logic circuits also exhibit very fast output switching due to this non-overlapping operation. In addition, dynamic logic circuits can be formed using moderately-sized transistors at the input, reducing input loading requirements.
Dynamic logic circuits represent an improvement over classic logic circuits, but still require a separate level shifting circuit in order to be used with load devices that operate within a different range of voltages. For example, if the dynamic logic circuit operates within a range of 0-1.8 volts and is to be used to drive a load device that operates within a range of 0-3.3 volts, a separate level shifting circuit would be required.
Accordingly, there is a strong desire and need to improve logic gates provided in integrated circuits by providing a combined dynamic logic gate having a non-overlapping operation and a level shifting circuit.
An apparatus and associated method are provided to improve the performance of logic gate circuits by combining dynamic logic circuit technology having a non-overlapping operation with level shifting circuit technology, thereby improving input loading, supply current, and switching speed characteristics.
In one aspect of the invention, a level shifting logic circuit is provided which includes a pair of logic gates each having an output and configured such that only one output of the pair is applied at a time to a respective one of a pair of output switching circuits coupled to receive the outputs of the logic gates, wherein a pair of inputs which transition in a first voltage range control the logic gates to produce an output which transitions in a second voltage range in response to the switching of the output switching circuits.
In another aspect of the invention, a method of operating a logic circuit is provided which includes providing first and second logic output signals transitioning within a first voltage range in response to at least one input logic signal which transitions within the first voltage range, providing at a logic circuit a third logic output signal which transitions within a second voltage range which differs from the first voltage range in response to first and second control signals applied as inputs to the logic circuit, and selectively applying the first and second logic output signals as the first and second control signals to the logic circuit in a manner which prevents simultaneous application of the first and second control signals to the logic circuit.